1. Field of the Invention
The present disclosure generally relates to the field of fabricating integrated circuits, and, more particularly, to forming capacitors in the metallization system, such as capacitors for dynamic random access memories (DRAMs), decoupling capacitors and the like.
2. Description of the Related Art
In modern integrated circuits, a very high number of individual circuit elements, such as field effect transistors in the form of CMOS, NMOS, PMOS elements, resistors, capacitors and the like, are formed on a single chip area. Typically, feature sizes of these circuit elements are steadily decreasing with the introduction of every new circuit generation, to provide currently available integrated circuits with high performance in terms of speed and/or power consumption. A reduction in size of transistors is an important aspect in steadily improving device performance of complex integrated circuits, such as CPUs. The reduction in size commonly brings about an increased switching speed, thereby enhancing signal processing performance while, however, increasing dynamic power consumption of the individual transistors. That is, due to the reduced switching time interval, the transient currents upon switching a MOS transistor element from logic low to logic high are significantly increased.
In addition to the large number of transistor elements, a plurality of passive circuit elements, such as capacitors, are typically formed in integrated circuits that are used for a plurality of purposes, such as charge storage for storing information, for decoupling and the like. Decoupling in integrated circuits is an important aspect for reducing the switching noise of the fast switching transistors, since the decoupling capacitor may provide energy at a specific point of the circuitry, for instance at the vicinity of a fast switching transistor, and thus reduce voltage variations caused by the high transient currents which may otherwise unduly affect the logic state represented by the transistor.
Due to the decreased dimensions of circuit elements, not only the performance of the individual transistor elements may be increased, but also their packing density may be improved, thereby providing the potential for incorporating increased functionality into a given chip area. For this reason, highly complex circuits have been developed which may include different types of circuits, such as analog circuits, digital circuits and the like, thereby providing entire systems on a single chip (SoC). Furthermore, in sophisticated micro-controller devices, an increasing amount of storage capacity may be provided on chip within the CPU core, thereby also significantly enhancing the overall performance of modern computer devices. For example, in typical micro-controller designs, different types of storage devices may be incorporated so as to provide an acceptable compromise between die area consumption and information storage density versus operating speed. For instance, fast or temporary memories, so-called cache memories, may be provided in the vicinity of the CPU core, wherein respective cache memories may be designed so as to allow reduced access times compared to external storage devices. Since a reduced access time for a cache memory may typically be associated with a reduced storage density thereof, the cache memories may be arranged according to a specified memory hierarchy, wherein a level 1 cache memory may represent the memory formed in accordance with the fastest available memory technology. For example, static RAM memories may be formed on the basis of registers, thereby enabling an access time determined by the switching speed of the corresponding transistors in the registers. Typically a plurality of transistors may be required so as to implement a corresponding static RAM cell, thereby significantly reducing the information storage density compared, for instance, to dynamic RAM (DRAM) memories including a storage capacitor in combination with a pass transistor. Thus, a higher information storage density may be achieved with DRAMs, although at an increased access time compared to static RAMs, which may nevertheless render dynamic RAMs attractive for specific less time-critical applications in complex semiconductor devices. For example, typical cache memories of level 3 may be implemented in the form of dynamic RAM memories so as to enhance information density within the CPU, while only moderately sacrificing overall performance.
Frequently, the storage capacitors may be formed in the transistor level using a vertical or planar configuration. While the planar architecture may require significant silicon area for obtaining the required capacitance values, the vertical arrangement may necessitate complex patterning regimes for forming the trenches of the capacitors.
For these reasons, in other approaches, capacitors may also be implemented in the metallization system of the semiconductor device, i.e., in the metallization layers comprising metal lines and vias, wherein, however, typically, significant modifications of the overall process flow may be required so as to implement the metal capacitors in the metallization system and to provide the corresponding interconnect structure for connecting the metal capacitors with the circuit elements in the device level, such as transistors and the like. Consequently, also in this case, additional process modules may have to be implemented into the overall process flow, which may thus contribute to additional process complexity.
In many cases, capacitive structures may be required in the immediate vicinity of circuit elements, such as transistors, which may be accomplished in some conventional approaches, for instance in view of providing a high bit density in dynamic RAM areas by providing deep trench capacitors in the semiconductor substrate and providing corresponding transistors in and around the deep trench capacitors. As pointed out above, although a space-efficient configuration may be achieved, nevertheless, extremely complicated processes, in particular for patterning the deep trenches for the capacitors in the semiconductor substrate, may be required, which may also be different for bulk devices and SOI devices, so that, in total, significant process-related variations may be introduced in complex semiconductor devices. On the other hand, providing the capacitors in the metallization system may provide additional interconnect complexity combined with sophisticated process modules for forming the capacitors independently from the regular metal interconnect structures.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.